C6: C Compiler Chain for Custom Configurable Computers

In the C6 project (KO Sept 2005) we develop a new soft processor core and associated compiler tool chain for low-cost FPGAs (in our case the 400K gates Xilinx Spartan-3). The primary motivation for the project is the need for a simple, yet powerful soft core that allows students to program FPGAs in embedded C in some of our labs. Rather than use an existing processor architecture, our independence of legacy issues allows us to rethink the entire C-to-FPGA concept. Instead of using a legacy core with some 90's or even 80's instruction set architecture (reflecting old technology), and retargeting a C compiler to this ISA, we start top down by choosing an ISA that is at (almost) the same high level as the intermediate RTL level within the compiler, with the VHDL core being thought of as a hardware interpretor of this ISA. Although a performance price is to be paid, both the compiler backend and the soft core can be kept at a minimum. Hence, the entire soft core + ANSI C compiler can be built in terms of merely one MS project (note that this includes a range of peripheral devices and full priority interrupt capabilities). The tool chain consists of the usual tools

• C compiler (the cross compiler, see above)
• Simulator (runs compiled code on host machine)
• Run-time system (libs + monitor on FPGA to upload and run)
• Real-time OS (currently we use UC/OS-II)
• Debugger (runs code on FPGA under supervision)
• Soft core (the VHDL microcontroller that runs the code on FPGA)

• the model helicopter embedded control application that we use in one of our labs (see course in4073)
• the DC electrical motor/encoder control application that we use in another lab (see course in2305-ii)

Publications

• Sijmen Woutersen, "The X32 Softcore: A Top-Down Approach to Processor Design", Master's Thesis Report, Nov 2006 pdf download
• Denis de Leeuw Duarte, "Algorithms in Silicon", Master's Thesis Report, May 2006. pdf download
• Denis de Leeuw Duarte, "Reconfigurable Computing: A Survey of Architectures and Synthesis Tools", Research Assignment Report, Oct. 2005. pdf download
• Michel Wilson, "Memory controller for a 6502 CPU in VHDL", BSc Thesis report, May 2006. pdf download
• Sijmen Woutersen, "Building a C Processor", Research Assignment Report, Dec. 2005. pdf download

Current Students:

• Mark Dufour (Teaching Assistent): Real-Time OS + lab applications + debugger + miscellaneous
• Tom Janssen (MSc student): heli controller design (PIC + FPGA/X32/UCOS)
• Michel Wilson (BSc student): 6502 soft core - external memory interface

• Denis de Leeuw (MSc student): C to VHDL compilation
• Sait Izmit (MSc student DCSC): floating point processing, signal filtering
• Willem Ridderhof (MSc student): USB interface (research assignment only)
• Awin Segobind (MSc student DCSC): heli controller application
• Sijmen Woutersen (MSc student, C compiler, simulator/debugger, VHDL soft core (an experimental 32 bit version, called X32, is currently under development and is slated for release in Sept 2006))